The invention relates to a plural-line CMOS semiconductor image sensor array device provided with sensor cells arranged in a matrix of coordinate-wise rows and columns, each cell comprising a photosensitive area, an output node, and a transfer gate for selectively interconnecting the photosensitive area and the output node, as being recited in the preamble of claim 1.
Such sensor arrays will represent useful tools for various types of imaging purposes, such as medical, hand-held telephone, surveyance and various others. Basically, there are two prime technologies, CCD and CMOS. Although both have particular pluses, the present invention focuses on CMOS cells. In particular, CMOS has a markedly lower noise potential for high-speed imaging. Furthermore, CMOS does not necessitate a noise versus bandwidth trade-off, since there can be multiple low-speed analog signal chains provided within a single CMOS die. It is to be noted that in this application CMOS means (C)MOS which implies that the semiconductor imaging sensor array device is based on CMOS (=Complimentary Metal Oxide Semiconductor) technology or on NMOS technology or on PMOS technology. In CMOS technology, which relates to the preferred embodiments, both NMOS and PMOS technology is used.
The present invention provides various aspects of use for plural-line sensor by having neighboring cell rows and columns lying close together without intervening gap strips other than necessary for electronic separation between neighbor rows and columns. By providing a limited amount of control circuitry within the cell area, flexibility of control will greatly be enhanced. This local circuitry may advantageously be combined with overall control facilities and/or separate data connections for the cells.
Furthermore, the invention does away with geometrical shift (notably a horizontal half pixel shift) between one array row and its next neighbor inasmuch as the present format would allow for various advantages both in design and operating of the array
By itself, U.S. Pat. No. 6,566,697 B1 published May 20, 2003, that shares one inventor with the present patent application and has been assigned to the present Assignee, discloses a PINNED PHOTODIODE FIVE TRANSISTOR PIXEL that can be used as a pixel building block for the present arrangement. In view of the prior art's extensive circuitry disclosure, the present text will consider most electronic signal aspects as being obvious to persons of average skill in the CMOS design art.
Furthermore, US Publication 2006/0284177 A1 published on Dec. 21, 2006, discloses a solid state image sensor with row-shared photodiodes. The present invention allows for a raised flexibility.